參數(shù)資料
型號: I74F257AN
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Quad 2-line to 1-line selector-multiplexer, non-inverting (3-State)
封裝: I74F257AD<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week 6, 2004,;I74F257AD<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week 6
文件頁數(shù): 2/10頁
文件大小: 89K
代理商: I74F257AN
Philips Semiconductors
Product specification
74F257A
Quad 2-line to 1-line selector/multiplexer, non-inverting
(3-State)
2
1995 Mar 31
853–0360 15059
FEATURES
Industrial range available (–40
°
C to +85
°
C)
Multifunction capability
Non-inverting data path
3-State outputs
See 74F258A for inverting version
DESCRIPTION
The 74F257A has four identical 2-input multiplexers with 3-State
outputs which select 4 bits of data from two sources uncer control of
a common Select (S) input. The I0a inputs are selected when the
common Select input is Low and the I1n inputs are selected when
the common Select input is High. Data appears at the outputs in true
non-inverted form from the selected inputs. The 74F257A is the logic
implementation of a 4-pole, 2-position switch where the position of
the switch is determined by the logic levels supplied to the common
Slect input. Outputs are forced to a high impedance “off” state when
the Output Enable (OE) is High. All but one device must be in high
impedance state to avoid currents that would exceed the maximum
rating if the outputs were tied together. Design of the Output Enable
signals must ensure that there is no overlap when outputs of 3-state
devices were tied together.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Yb
V
CC
Yd
I0c
I1c
I1d
OE
I0d
S
I0a
I1b
I1a
Ya
I0b
9
8
GND
Yc
SF00673
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F257A
4.3ns
12mA
ORDERING INFORMATION
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F257AN
INDUSTRIAL RANGE
V
CC
= 5V
±
10%, T
amb
= –40
°
C to +85
°
C
I74F257AN
16-pin plastic DIP
SOT38-4
16-pin plastic SO
N74F257AD
I74F257AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
I0n, I1n
Data inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
S
Common Select input
1.0/1.0
OE
Output Enable input (active Low)
1.0/1.0
Ya – Yd
Data outputs
150/33
3.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
V
= Pin 16
GND = Pin 8
SF00674
1
15
S
OE
2
3
5
6
11
10
14
I0a
I1a
I0b
I1b
I0c
I1c
I0d
Ya
Yb
Yc
Yd
4
7
9
12
13
I1d
LOGIC SYMBOL (IEEE/IEC)
SF00675
2
1
15
EN
1
G1
3
4
1
MUX
5
6
7
10
11
9
13
14
12
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