
Page 1 of 10
I
A16450
Universal Asynchronous Receiver/Transmitter
Preliminary Data Sheet
FEATURES
Form, Fit, and Function Compatible with the National
NS16450
Packaging options available: 40 Pin Plastic or 44 Pin Plastic Leaded Chip
Carrier
Programmable Word Length, Stop Bits, and Parity
Full Duplex Operation
Programmable Baud Rate Generator
-
Division of any input clock by 1 to (2
16
–1)
-
Generates Internal 16 x clock
Programmable Serial-Interface
-
5-, 6-, 7- or 8-bit characters
-
Even, Odd, or No-Parity Bit Generation and Detection
-
1-, 1 -, or 2-Stop Bit Generation
-
Baud Generation of DC to 56k
Prioritized Interrupt Control
Internal Diagnostic/Loopback Capabilities
Copyright
1999, InnovASIC Inc.
Customer SpecficIC Soutions
The IA16450 uses
innov
ASIC
’s innovative new
f
3
Program
to provide industry with parts that
other vendors have declared obsolete. By specifying parts through this program a customer is
assured of never having a component become obsolete again. This advanced information sheet
assumes the original part has been designed in, and so provides a summary of capabilities only. For
new designs contact
innov
ASIC
for more detailed information.
National is a copyright trademark of National Semiconductor Corporation
Package Pinout
44 Pin LCC
IA16450
(12)
N. C.
(7)
D5
(8)
D6
(9)
D7
(10)
RCLK
(11)
SIN
(13)
SOUT
(14)
CS0
(15)
CS1
(16)
CS2_n
(17)
BAUDOUT_n
MR
INTR
N. C.
OUT2_n
DTR_n
OUT1_n
W
X
X
(
(
(
(
(
(
(
(
(
D
(
D
(
C
D
D
(34)
(39)
(38)
(37)
(36)
(35)
(33)
(32)
(31)
(30)
(29)
(
(
(
(
(
(
(
(
(
(
(
V
R
D
N
D
D
V
W
R
N
D
R
A
C
A2
A1
A0
N. C.
RTS_n
(6)
(1)
(2)
(3)
(4)
(5)
(7)
(8)
(9)
RCLK
(10)
SIN
(11)
SOUT
(12)
CS0
(13)
CS1
CS2_n
(14)
40 Pin DIP
IA16450
RTS_n
OUT2_n
INTR
N. C.
(20)
VSS
(15)
BAUDOUT_n
(16)
XIN
(17)
XOUT
(18)
WR_n
(19)
WR
(21)
(22)
(23)
(24)
RD
RD_n
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
CSOUT
DDIS
A2
ADS_n
A0
A1
OUT1_n
DTR_n
CTS_n
MR
DCD_n
DSR_n
VCC
RI_n
D5
D0
D1
D2
D3
D4
D6
D7