- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379200 > IA16450-PDW40I (Innovasic Semiconductor) Universal Asynchronous Receiver/Transmitter PDF資料下載
參數(shù)資料
| 型號(hào)： | IA16450-PDW40I |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | Universal Asynchronous Receiver/Transmitter |
| 中文描述： | 通用異步接收器/發(fā)送器 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | IA16450-PDW40I |
Page 3 of 10
I
A16450
Universal Asynchronous Receiver/Transmitter
Preliminary Data Sheet
Copyright
1999, InnovASIC Inc.
Customer SpecficIC Soutions
I/O Signal Description
Table 1 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided
.
Table 2 refers to the address
register map. Table 3 refers to the Preliminary A. C. Characteristics. Figure 2 illustrates the
Preliminary Timing Waveforms for this device. Environmental/Qualification Levels are listed in
Table 4.
Table 1
Name
Type
Description
MR
I
Master Reset - Active high - Clears all registers (except the
receiver buffer, transmitter holding and divisor latches) to their
initial state. Resets internal control logic to its initial state
A(2:0)
I
Register Address - Active high - This bus selects one of the
internal UART registers (refer to table 1). Note the state of the
divisor latch access bit (DLAB - the msb of the line control
register) must be set high to access the divisor latches and low
to access the receiver buffer or the interrupt enable register.
DIN(7:0)
I
Data Input Bus - Active high - Serves as input data when
writing to internal UART registers.
CS0
I
Chip Select 0 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
CS1
I
Chip Select 1 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
CS2_n
I
Chip Select 2 - Active low - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
ADS_n
I
Address Strobe - Active low - Gating signal to the Address
input latch. The positive edge of ADS_n latches the state of the
register address bus into the Address input latch. If address
signals are guaranteed to be stable for the duration of a read or
write cycle, ADS_n may be tied low thus forcing the Address
input latch to be transparent.
RD
I
Read Control - Active High - when RD is high or RD_n is low
and the UART is selected, read transactions from internal
UART registers are possible.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IA16450 | Universal Asynchronous Receiver/Transmitter |
| IA16450-PLC44C | Universal Asynchronous Receiver/Transmitter |
| IA16450-PLC44I | Universal Asynchronous Receiver/Transmitter |
| IA186ES-TQF100I | 16-BIT MICROCONTROLLERS |
| IA188ES-PQF100I | 16-BIT MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IA16450-PLC44C | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:Universal Asynchronous Receiver/Transmitter |
| IA16450-PLC44I | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:Universal Asynchronous Receiver/Transmitter |
| IA167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:雙通道視頻放大IC. |
| IA171 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:四級(jí)低通濾波視頻放大IC |
| IA175 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。