參數資料
型號: IBIS4-6600-C-1
廠商: Cypress Semiconductor Corp.
英文描述: High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
中文描述: 高像素分辨率6.6米,卷簾門的CMOS圖像傳感器
文件頁數: 40/63頁
文件大?。?/td> 1286K
代理商: IBIS4-6600-C-1
IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 40 of 63
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Figure 22: Basic frame and line timing.
The pulse width of Y_
CLOCK
should be minimum 1 clock cycle and 3 clock cycles for
Y_
START
. As long as Y_
CLOCK
is applied, the sequencer stays in a suspended state.
T
1
Row blanking time: During this period, the X-sequencer generates the control
signals to sample the pixel signal and pixel reset levels, and start the readout
of one line. It depends on the granularity of the X-sequencer clock (see Table
14).
T
2
Pixels counted by pixel counter until the value of N
ROF
_
PIXELS
register is
reached. P
IXEL
_
VALID
goes high when the internal X_
SYNC
signal is
generated, in other words when the readout of the pixels is started.
P
IXEL
_
VALID
goes low when the pixel counter reaches the value loaded in the
N
ROF
_
PIXELS
register. E
OL
goes high S
YS
_
CLOCK
cycle after the falling edge
of P
IXEL
_
VALID
.
T
3
E
OF
goes high when the line counter reaches the value loaded in the
N
ROF
_
LINES
register and the line is read (P
IXEL
_
VALID
goes low).
Both E
OF
and E
OL
can be tied to Y_
START
(E
OF
) and Y_
CLOCK
(E
OL
) if both signals
are delayed with at least 2 S
YS
_
CLOCK
periods to let the sensor run in a fully
automatic way.
4.3 Pixel output timing
4.3.1 Two outputs
The pixel signal at the O
UT
1 (O
UT
2) output becomes valid after 4 S
YS
_
CLOCK
cycles
when the internal X_
SYNC
(= start of P
IXEL
_
VALID
output) has appeared (see Figure
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