參數(shù)資料
型號(hào): IBIS4-6600-C-2
廠商: Cypress Semiconductor Corp.
英文描述: High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
中文描述: 高像素分辨率6.6米,卷簾門的CMOS圖像傳感器
文件頁數(shù): 34/63頁
文件大?。?/td> 1286K
代理商: IBIS4-6600-C-2
IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 34 of 63
3901 North First Street
San Jose, CA 95134
408-943-2600
Sync of left
shift-register
Sync of right
shift-register
Line n
T
reg_int
Last line, followed by sync
of left shift-register
T
int
Sync
Figure 18: Syncing of the Y-shift registers.
T
reg_int
Difference between left and right pointer = integration counter until value “n”
of I
NT
_
TIME
register is reached = I
NT
_
TIME
register.
In case of NDR = 0, the actual integration time T
int
is given by
T
int
Integration time [# lines] = N
ROF
_
LINES
register - I
NT
_
TIME
register + 1
In case of NDR = 1, NDR mode 1, the time T
int
between two readings of the same row
is given by
T
int
Integration time [# lines] = N
ROF
_
LINES
register + 1
In case of NDR = 1, NDR mode 2, the times T
int1
and T
int2
between two readings of
the same row (alternatingly) are given by
T
int1
Integration time [# lines] = 2 * I
NT
_
TIME
register + 1
T
int2
Integration time [# lines]
= 2 * (N
ROF
_
LINES
register + 1) – (2 * I
NT
_
TIME
register + 1)
3.9.2.e
D
ELAY
register
The D
ELAY
register can be used to delay the P
IXEL
_
VALID
pulse (bits 0:3) and the
EOL/EOF pulses (bits 4:7) to synchronize them to the real pixel values at the analog
output or the ADC output (which give additional delays depending on their settings).
The bit settings and corresponding delay is indicated in Table 15.
Table 15: Delay added by changing the settings of the D
ELAY
register
bits
0000
0001
0010
0011
0100
0101
Delay [# S
YS
_
CLOCK
periods]
0
0
0
1
2
3
bits
1000
1001
1010
1011
1100
1101
Delay [# S
YS
_
CLOCK
periods
]
6
7
8
9
10
11
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PDF描述
IBIS4-6600-M-1 High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
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