參數(shù)資料
型號(hào): IBIS4-6600-C-2
廠商: Cypress Semiconductor Corp.
英文描述: High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
中文描述: 高像素分辨率6.6米,卷簾門的CMOS圖像傳感器
文件頁(yè)數(shù): 44/63頁(yè)
文件大?。?/td> 1286K
代理商: IBIS4-6600-C-2
IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 44 of 63
3901 North First Street
San Jose, CA 95134
408-943-2600
Pin Pin name
Pin
type
Expected
Voltage [V]
Pin description
17
CMD_FS_ADC
Input
0.73
Biasing of first stage ADC. Connect to
VDDA_ADC with R = 50 k
and
decouple to GNDA_ADC with C = 100
nF.
Biasing of second stage ADC. Connect
to VDDA_ADC with R = 50 k
and
decouple to GNDA_ADC.
Biasing of input stage ADC. Connect to
VDDA_ADC with R = 180 k
and
decouple to GNDA_ADC with C = 100
nF.
GND (&substrate) of analog output.
18
CMD_SS_ADC
Input
0.73
19
CMD_AMP_ADC
input
0.59
20
GNDAMP
Ground 0
21
OUT1
Output
Black level: 1
@ code 190
D
AC
_
RAW
reg.
Analog output 1.
22
ADC_IN1
Input
See OUT1.
Analog input ADC 1.
VDD of analog output [2.5 V] (Can be
connected to VDDA).
23
VDDAMP
Power
2.5
24
OUT2
Output
Black level: 1
@ code 190
D
AC
_
RAW
reg.
See OUT2.
2.5
0
0
2.5
Analog output 2.
25
26
27
28
29
ADC_IN2
VDDD
GNDD
GNDA
VDDA
Input
Power
Power
Power
Power
Analog input ADC 2.
VDD of digital part [2.5 V].
GND (&substrate) of digital part.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
Register clock. Data on internal bus is
copied to corresponding registers on
rising edge.
System clock defining the pixel rate.
Global system reset.
Line clock.
Start frame readout.
GND (&substrate) of digital part ADC.
VDD of digital part [2.5 V] ADC.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
ADC high reference voltage (e.g.
connect to VDDA_ADC with R = 144
and decouple to GNDA_ADC with C
= 100 nF.
ADC low reference voltage (e.g.
connect to GNDA_ADC with R = 59
and decouple to GNDA_ADC with C =
100 nF.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
GND (&substrate) of digital part ADC.
VDD of digital part [2.5 V] ADC.
30
REG_CLOCK
Input
-
31
32
33
34
35
36
37
38
SYS_CLOCK
SYS_RESET
Y_CLK
Y_START
GNDD_ADC
VDDD_ADC
GNDA_ADC
VDDA_ADC
Input
Input
Input
Input
Power
Power
Power
Power
-
-
-
-
0
2.5
0
2.5
39
VHIGH_ADC
Input
2.37
40
VLOW_ADC
Input
0.59
41
42
43
44
GNDA_ADC
VDDA_ADC
GNDD_ADC
VDDD_ADC
Power
Power
Power
Power
0
2.5
0
2.5
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