參數(shù)資料
型號(hào): IBIS4-6600-M-1
廠商: Cypress Semiconductor Corp.
英文描述: High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
中文描述: 高像素分辨率6.6米,卷簾門的CMOS圖像傳感器
文件頁數(shù): 36/63頁
文件大?。?/td> 1286K
代理商: IBIS4-6600-M-1
IBIS4-6600
Datasheet
3.9.2.i.4
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 36 of 63
3901 North First Street
San Jose, CA 95134
408-943-2600
Standby
If S
TANDBY
= 1, the complete output amplifier is put in standby (this reduces the
power consumption significantly)
3.9.2.i.5
Delay_clk_amp
The clock that acts on the output amplifier can be delayed to compensate for any
delay that is introduced in the path from shift register, column selection logic, column
amplifier and busses to the output amplifier. Setting ‘000’ is used as a baseline.
Table 16: Delay added by changing the settings of the D
ELAY
_
CLK
_
AMP
bits
bits Delay [ns] bits
000
1.7
001
2.9
010
4.3
011
6.1
Delay [ns]
Inversion + 8.3
Inversion + 9.7
Inversion + 11.1
Inversion + 12.3
100
101
110
111
3.9.2.j
D
AC
_
RAW
_
REG
and
D
AC
_
FINE
_
REG
register
These registers determine the black reference level at the output of the output
amplifier. Bit setting 11111111 for D
AC
_
RAW
_
REG
register gives the highest offset
voltage; bit setting 00000000 for D
AC
_
RAW
_
REG
register gives the lowest offset
voltage. Ideally, if the two output paths have no offset mismatch, the D
AC
_
FINE
_
REG
register must be set to 10000000. Deviation from this value can be used to
compensate the internal mismatch (see 3.5.4).
3.9.2.k
D
AC
_
RAW
_
DARK
register
This register determines the voltage level that is put on the internal busses during
calibration of the output stage. This voltage level is also continuously put on the reset
busses in case of non-destructive readout (as a reset level for the double sampling
FPN correction).
3.9.2.l
A
DC
register
3.9.2.l.1
Standby_1 and standby_2
In case only one or none of the ADCs is used, the other or both ADCs can be put in
standby by setting the bit to 1 (this reduces the power consumption significantly).
3.9.2.l.2
One
In case O
UT
1 and O
UT
2 are both used and connected to A
DC
_
IN
1 and A
DC
_
IN
2
respectively, O
NE
must be 0 to use both ADCs and to multiplex their output to
A
DC
_
D
<9:0>. If O
NE
= 1, the multiplexing is disabled.
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