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參數(shù)資料
| 型號： | IBIS4-6600-M-1 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| 中文描述： | 高像素分辨率6.6米，卷簾門的CMOS圖像傳感器 |
| 文件頁數(shù)： | 45/63頁 |
| 文件大?。?/td> | 1286K |
| 代理商： | IBIS4-6600-M-1 |
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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 45 of 63
3901 North First Street
San Jose, CA 95134
408-943-2600
Pin Pin name
Pin
type
Expected
Voltage [V]
2.5 (for no
dual slope)
-
Pin description
45
VDD_RESET_DS
Power
Variable reset voltage (dual slope).
46
ADC_CLK_EXT
Input
External ADC clock.
Diagnostic end of line signal (produced
by sequencer), can be used as Y_CLK.
Diagnostic end of frame signal
(produced by sequencer), can be used
as Y_START.
Diagnostic signal. High during pixel
readout.
Temperature measurement. Output
voltage varies linearly with
temperature.
ADC data output (MSB).
VDD of pixel core [2.5 V].
Anti-blooming ground. Set to 1 V for
improved anti-blooming behavior.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
Reset voltage [2.5 V]. Highest voltage
to the chip. 3.3 V for extended dynamic
range or ‘hard reset’.
ADC data output.
ADC data output.
ADC data output (LSB).
Boundary scan (allows debugging of
internal nodes): reset.
Boundary scan (allows debugging of
internal nodes): clock.
Boundary scan (allows debugging of
internal nodes): in.
Boundary scan (allows debugging of
internal nodes): bus.
Biasing of X and Y decoder. Connect
to VDDD with R = 50 k
and decouple
to GNDD with C = 100 nF.
47
EOL
Output
-
48
EOF
Output
-
49
PIX_VALID
Output
-
50
TEMP
Output
-
51
52
ADC_D<9>
VDD_PIX
Output
Power
-
2.5
53
GND_AB
Power
0
54
55
56
57
58
59
ADC_D<8>
ADC_D<7>
ADC_D<6>
ADC_D<5>
ADC_D<4>
ADC_D<3>
Output
Output
Output
Output
Output
Output
-
-
-
-
-
-
60
VDD_RESET
Power
2.5
61
62
63
ADC_D<2>
ADC_D<1>
ADC_D<0>
Output
Output
Output
-
-
-
64
BS_RESET
Input
-
65
BS_CLOCK
Input
-
66
BS_DIN
Input
-
67
BS_BUS
Output
-
68
CMD_DEC
Input
0.74
Note on power-on behavior
At power-on, the chip is in an undefined state. It is advised that the power-on is
accompanied by the assertion of the S
YS
_
CLOCK
and a S
YS
_
RESET
pulse that puts all
internal registers in their default state (all bits are set to 0). The X-shift registers are in
a defined state after the first X_
SYNC
which occurs a few microseconds after the first
Y_
START
and
Y_
CLOCK
pulse. Prior to this X_
SYNC
, the chip may draw more current
from the analog power supply V
DDA
. It is therefore favorable to have separate analog
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