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| 型號(hào)： | IBIS4-6600 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| 中文描述： | 高像素分辨率6.6米，卷簾門的CMOS圖像傳感器 |
| 文件頁數(shù)： | 37/63頁 |
| 文件大小： | 1286K |
| 代理商： | IBIS4-6600 |
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IBIS4-6600
Datasheet
3.9.2.l.3
Cypress Semiconductor Corporation
Contact: info@Fillfactory.com Document #: 38-05708 Rev.**(Revision 1.3 ) Page 37 of 63
3901 North First Street
San Jose, CA 95134
408-943-2600
Switch
In case the two ADCs are used (O
NE
= 0) and internal pixel clock (E
XT
_
CLK
= 0), the
ADC output is delayed with one system clock cycle if S
WITCH
= 1. In case the two
ADCs are used (O
NE
= 0) and an external ADC clock (E
XT
_
CLK
= 1) is applied, the
ADC output is delayed with half ADC clock cycle if S
WITCH
= 1.
In case only one ADC is used, the digital multiplexing is disabled by O
NE
= 1, but
S
WITCH
selects which ADC output is on ADC_D<9:0> (S
WITCH
= 0: ADC_1,
S
WITCH
= 1: ADC_2).
3.9.2.l.4
Ext_clk
In case E
XT
_
CLK
= 0, the internal pixel clock (that drives the X-shift registers and
output amplifier, i.e. half the system clock) is used as input for the ADC clock. In case
E
XT
_
CLK
= 1, an external clock must be applied to pin A
DC
_
CLK
_
EXT
(pin 46).
3.9.2.l.5
Tristate
In case T
RISTATE
= 1, the A
DC
_
D
<9:0> outputs are in tri-state mode.
3.9.2.l.6
Delay_clk_adc
The clock that finally acts on the ADCs can be delayed to compensate for any delay
that is introduced in the path from the analog outputs to the input stage of the ADCs.
The same settings apply as for the delay that can be given to the clock acting on the
output amplifier (see Table 16). The best setting will also depend on the delay of the
output amplifier clock and the load of the output amplifier. It must be used to
optimize the sampling moment of the ADCs with respect to the analog pixel input
signals. Setting ‘000’ is used as a baseline.
3.9.2.l.7
Gamma
If G
AMMA
is set to 0, the ADC input to output conversion is linear, otherwise the
conversion follows a ‘gamma’ law (more contrast in dark parts of the window, lower
contrast in the bright parts).
3.9.2.l.8
Bitinvert
If B
ITINVERT
= 0, 0000000000 is the conversion of the lowest possible input voltage,
otherwise the bits are inverted.
3.9.3 Serial to Parallel interface
To upload the sequencer registers a dedicated serial to parallel interface (SPI) is
implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The
address must be uploaded first (MSB first), then the data (also MSB first).
相關(guān)PDF資料 |
PDF描述 |
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| IBIS4-6600-C-1 | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| IBIS4-6600-C-2 | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| IBIS4-6600-M-1 | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| IBIS4-6600-M-2 | High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor |
| IBM0116400B | 4M x 4 12/10 DRAM(16M位 動(dòng)態(tài)RAM（帶22條地址線，其中12條為行地址選通，10條為列地址選通）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBIS4-6600_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:6.6 MP CMOS Image Sensor |
| IBIS4-6600-C-1 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR COLOR CMOS 2210X3002PIXELS 68PIN LCC - Bulk |
| IBIS4-6600-C-2 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR COLOR CMOS 2210X3002PIXELS 68PIN LCC - Bulk |
| IBIS4-6600-EVAL | 制造商:Cypress Semiconductor 功能描述:IND.HI-PERF CMOS IMAGE SENSOR EVAL BOARD. (COLOR OR MONO) - Bulk |
| IBIS4-6600-M-1 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR MONOCHROME CMOS 2210X3002PIXELS 68PIN LCC - Bulk |
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