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參數(shù)資料
| 型號： | IBM11M2640H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 DRAM Module(2M x 64 動態(tài)RAM模塊) |
| 中文描述： | 200萬× 64內(nèi)存（2米× 64動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 480K |
| 代理商： | IBM11M2640H |
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IBM11M2640H
IBM11M2640HB
2M x 64 DRAM MODULE
64G1559
SA14-4612-04
Revised 5/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 25 of 26
Revision Log
Rev
Contents of Modification
08/93
Initial release of 2Mx64 DIMM spec.
7/94
Split x64 and x72 DIMM specifications.
- Significant text modifications to all areas of specification.
7/95
Updated Ordering Information
Added Hidden Refresh
Updated Block Diagram
Added Overshoot/Undershoot information
Added PD/ID capacitance; added PDE note 3 to PD table
Improved timings (
t
ASR,
t
ASC,
t
RAD,
t
AA,
t
RAL,
t
CAL,
t
AWD
)
1/96
Added 3.3V product
3/96
Added timing: t
CAS
Improved power dissipation
Improved DC electrical characteristics: I
CC1,
I
CC3,
I
CC4,
I
CC6
Improved timings: t
CAH,
t
CRP,
t
DH,
t
RRH,
t
OEZ,
t
CDD,
t
OFF,
t
OEH
The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
Hidden Refresh Cycle (Read) timing diagram was changed to show data being turned off with CAS not RAS
5/96
Updated ordering information
Discontinued (9/98 - last order; 3/99 last ship)
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