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| 型號(hào)： | IBM11M2730HB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 72 DRAM Module(2M x 72 動(dòng)態(tài)RAM模塊) |
| 中文描述： | 200萬× 72內(nèi)存（2米× 72動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 502K |
| 代理商： | IBM11M2730HB |
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IBM11M2730H
IBM11M2730HB
2M x 72 DRAM MODULE
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 26
64G1556
SA14-4610-03
Revised 5/96
Write Cycle
Symbol
Parameter
-60
-70
Unit
Notes
Min
Max
Min
Max
t
WCS
Write Command Set Up Time
2
—
2
—
ns
1
t
WCH
Write Command Hold Time
17
—
17
—
ns
t
WP
Write Command Pulse Width
15
—
15
—
ns
t
RWL
Write Command to RAS Lead Time
20
—
25
—
ns
t
CWL
Write Command to CAS Lead Time
17
—
22
—
ns
t
WCR
Write Command Hold Time Referenced to RAS
—
—
—
—
ns
2
t
DHR
Data Hold Time Referenced to RAS
—
—
—
—
ns
2
t
DS
D
IN
Setup Time
-2
—
-2
—
ns
3
t
DH
D
IN
Hold Time
17
—
20
—
ns
3
1. t
WCS
, t
RWD
, t
CWD
, t
AWD
, and t
CPW
are not restrictive parameters. They are included in the data sheet as electrical characteristics
only. If t
WCS
≥
t
WCS
(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through
the entire cycle; If t
RWD
≥
t
RWD
(min.), t
CWD
≥
t
CWD
(min.), t
AWD
≥
t
AWD
(min.) and t
CPW
≥
t
CPW
(min.)(Fast Page Mode), the cycle is a
Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the
condition of the data (at access time) is indeterminate.
2. This timing parameter is not applicable to this product, but applies to a related product in this family.
3. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE.
Discontinued (9/98 - last order; 3/99 last ship)
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