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參數(shù)資料
| 型號： | IBM11M4640C |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 DRAM MODULE(4M x 64 工業(yè)標(biāo)準(zhǔn)的168腳8位動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4米× 64的DRAM模組（4米× 64工業(yè)標(biāo)準(zhǔn)的168腳8位動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 518K |
| 代理商： | IBM11M4640C |
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IBM11M4640C
IBM11M4640CB
4M x 64 DRAM MODULE
03H7156
SA14-4609-04
Revised 5/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 25 of 26
Revision Log
Rev
Contents of Modification
8/93
Release of 4Mx64 and 4Mx72 DIMM specs using x1 and x4 DRAMs.
7/94
Split x64 and x72 DIMM specifications.
- Significant text modifications to all areas of specification.
- Capacitance values modified.
7/95
Updated Ordering Information
Added Hidden Refresh
Updated Block Diagram
Added Overshoot/Undershoot information
Added PD/ID capacitance; added PDE note 3 to PD table
Improved timings (
t
ASR,
t
ASC,
t
RAD,
t
AA,
t
RAL,
t
CAL,
t
AWD)
1/96
Added 3.3V product
Improved timings: t
CAH,
t
CHR,
t
CSR
3/96
Added timing: t
CAS
Improved power dissipation
Improved DC electrical characteristics: I
CC1,
I
CC3,
I
CC4,
I
CC6
Improved timings: t
CAH,
t
CRP,
t
DH,
t
OEZ,
t
CDD,
t
OFF,
t
OEH
The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
Hidden Refresh Cycle (Read) timing diagram was changed to show data being turned off with CAS not RAS
5/96
Updated ordering information
Discontinued (9/98 - last order; 3/99 last ship)
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