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參數(shù)資料
| 型號： | IBM11M4730CF |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| 中文描述： | 4米× 72內(nèi)存（4米× 72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 26/27頁 |
| 文件大?。?/td> | 500K |
| 代理商： | IBM11M4730CF |
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IBM11M4730CB
IBM11M4730CF
4M x 72 DRAM Module
IBM11M4730CH
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 27
64G1557.E20999D
Revised 4/98
Revision Log
Rev
Contents of Modification
8/93
Initial Release.
7/94
Significant text modifications to all areas of specification.
7/95
Combined 3.3V/5.5V products into same specification
Updated Ordering Information
Added Hidden Refresh
Added Overshoot/Undershoot information
Added PD/ID capacitance; added PDE note 3 to PD table
Improved timings (
t
ASR,
t
ASC,
t
RAD,
t
AA,
t
RAL,
t
AWD)
Updated Layout Drawing
8/96
Updated ordering information
Improved power dissipation
Added timing: t
CAS,
t
CAL,
t
CPW
Deleted timing: t
ROH
Improved DC electrical characteristics: I
CC1,
I
CC3,
I
CC4,
I
CC6
Improved timings: t
CAH,
t
CRP,
t
DH,
t
RRH,
t
OEZ,
t
CDD,
t
OFF,
t
OEH,
t
CSR,
t
CHR
The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
Hidden Refresh Cycle (Read) timing diagram was changed to show data being turned off with CAS not RAS
8/96
Updated ordering information
Corrected assembly drawing
4/98
Updated ordering information
Deleted 70ns offering
Discontinued (9/98 - last order; 3/99 last ship)
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