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參數(shù)資料
| 型號： | IBM11M4730H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| 中文描述： | 4米× 72內存（4米× 72動態(tài)內存模塊） |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 512K |
| 代理商： | IBM11M4730H |
IBM11M4730H
IBM11M4730HB
4M x 72 DRAM MODULE
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 25
54H8529
SA14-4637-02
Released 12/96
Fast Page Mode Cycle
Symbol
Parameter
-60
-70
Unit
Notes
Min
Max
Min
Max
t
PC
Fast Page Mode Cycle Time
40
—
45
—
ns
t
RASP
Fast Page Mode RAS Pulse Width
60
100K
70
100K
ns
t
CPRH
RAS Hold Time from CAS Precharge
40
—
45
—
ns
t
CPA
Access Time from CAS Precharge
—
40
—
45
ns
1, 2
1. Measured with the specified current load and 100pF.
2. Access time is determined by the latter of t
RAC
, t
CAC
, t
CPA
, t
AA,
t
OEA
.
Read-Modify-Write Cycle
Symbol
Parameter
-60
-70
Unit
Notes
Min
Max
Min
Max
t
RWC
Read-Modify-Write Cycle Time
158
—
188
—
ns
t
RWD
RAS to WE Delay Time
83
—
98
—
ns
1
t
CWD
CAS to WE Delay Time
45
—
55
—
ns
1
t
AWD
Column Address to WE Delay Time
58
—
68
—
ns
1
t
OEH
OE Command Hold Time
15
—
15
—
ns
1. t
WCS
, t
RWD
, t
CWD
, t
AWD
, and t
CPW
are not restrictive parameters. They are included in the data sheet as electrical characteristics
only. If t
WCS
≥
t
WCS
(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through
the entire cycle; If t
RWD
≥
t
RWD
(min.), t
CWD
≥
t
CWD
(min.), t
AWD
≥
t
AWD
(min.) and t
CPW
≥
t
CPW
(min.)(Fast Page Mode), the cycle is a
Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the
condition of the data (at access time) is indeterminate.
Fast Page Mode Read-Modify-Write Cycle
Symbol
Parameter
-60
-70
Unit
Min
Max
Min
Max
t
PRWC
Fast Page Mode Read-Modify-Write Cycle Time
83
—
98
—
ns
t
CPW
WE Delay time from CAS Precharge
63
—
73
—
ns
Discontinued (9/98 - last order; 3/99 - last ship)
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