參數(shù)資料
型號： IBM11M4730H
廠商： IBM Microeletronics
英文描述： 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊)
中文描述： 4米× 72內(nèi)存（4米× 72動態(tài)內(nèi)存模塊）
文件頁數(shù)： 7/26頁
文件大?。?/td> 512K
代理商： IBM11M4730H
IBM11M4730H
IBM11M4730HB
4M x 72 DRAM MODULE
54H8529
SA14-4637-02
Released 12/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 25
AC Characteristics
(TA = 0 to +70
°
C, Vcc = 3.3V
±
0.3V or 5.0V
±
0.5V)
1. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and
V
IL
.
2. An initial pause of 200
μ
s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the
Dram device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 60ns and
70ns.
4. AC measurements assume t
T
= 5ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-60
-70
Unit
Notes
Min
Max
Min
Max
t
RC
Random Read or Write Cycle Time
110
—
130
—
ns
t
RP
RAS Precharge Time
40
—
50
—
ns
t
CP
CAS Precharge Time
10
—
10
—
ns
t
RAS
RAS Pulse Width
60
10K
70
10K
ns
t
CAS
CAS Pulse Width
15
10K
20
10K
ns
1
t
ASR
Row Address Setup Time
5
—
5
—
ns
t
RAH
Row Address Hold Time
8
—
8
—
ns
t
ASC
Column Address Setup Time
2
—
2
—
ns
t
CAH
Column Address Hold Time
10
—
10
—
ns
t
RCD
RAS to CAS Delay Time
18
40
18
45
ns
2
t
RAD
RAS to Column Address Delay Time
13
25
13
30
ns
3
t
RSH
RAS Hold Time
20
—
25
—
ns
t
CSH
CAS Hold Time
58
—
68
—
ns
t
CRP
CAS to RAS Precharge Time
10
—
10
—
ns
t
ODD
OE to D
IN
Delay Time
20
—
25
—
ns
4
t
DZO
OE Delay Time from D
IN
-2
—
-2
—
ns
5
t
DZC
CAS Delay Time from D
IN
-2
—
-2
—
ns
5
t
AR
Column Address Hold Time Referenced to RAS
—
—
—
—
—
6
t
T
Transition Time (Rise and Fall)
3
30
3
30
ns
1. The minimum t
CAS
requires t
CSH
to be met for both writes and reads. Also, because of the buffer, the minimum t
CAS
for a read cycle
must be extended to guarantee the data out window (t
OH
) in the application. For example, a t
CAS
of 15ns plus a minimum t
OH
of 2ns
would result in turning data out of the DIMM at 17ns (3ns before max t
CAC
of 20ns).
2. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
3. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
4. Either t
CDD
or t
ODD
must be satisfied.
5. Either t
DZC
or t
DZO
must be satisfied.
6. This timing parameter is not applicable to this product, but applies to a related product in this family.
Discontinued (9/98 - last order; 3/99 - last ship)
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