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IBM11M4735HB
4M x 72 DRAM MODULE
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 27
75H5409
GA14-4639-00
Revised 11/96
Write Cycle
Symbol
Parameter
-60
Unit
Notes
Min
Max
t
WCS
Write Command Set Up Time
2
—
ns
1
t
WCH
Write Command Hold Time
12
—
ns
t
WP
Write Command Pulse Width
10
—
ns
t
RWL
Write Command to RAS Lead Time
15
—
ns
t
CWL
Write Command to CAS Lead Time
12
—
ns
t
DS
D
IN
Setup Time
-2
—
ns
2
t
DH
D
IN
Hold Time
15
—
ns
2
1. t
WCS
, t
RWD
, t
CWD
, and t
AWD
are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle; If t
RWD
≥
t
RWD
(min.), t
CWD
≥
t
CWD
(min.)and t
AWD
≥
t
AWD
(min.), the cycle is a Read-Modify-Write cycle and the data will
contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is
indeterminate.
2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE.
Read Cycle
Symbol
Parameter
-60
Unit
Notes
Min
Max
t
RAC
Access Time from RAS
—
60
ns
1, 2
t
CAC
Access Time from CAS
—
20
ns
1, 2
t
AA
Access Time from Address
—
35
ns
1, 2
t
OEA
Access Time from OE
—
20
ns
1, 2
t
RCS
Read Command Setup Time
2
—
ns
t
RCH
Read Command Hold Time to CAS
2
—
ns
3
t
RRH
Read Command Hold Time to RAS
0
—
ns
3
t
RAL
Column Address to RAS Lead Time
35
—
ns
t
CLZ
CAS to Output in Low-Z
2
—
ns
t
OES
OE setup time prior to CAS
10
—
ns
t
ORD
OE setup time prior to RAS (Hidden Refresh)
5
—
ns
t
CDD
CAS to D
IN
Delay Time
20
—
ns
5
t
OEZ
Output Buffer Turn-off Delay from OE
2
20
ns
4
t
OFF
Output Buffer Turn-off Delay
2
20
ns
4, 6
1. Measured with the specified current load and 100pF.
2. Access time is determined by the latter of t
RAC
, t
CAC
, t
CPA
, t
AA,
t
OEA
.
3. Either t
RCH
or t
RRH
must be satisfied.
4. t
OFF
(max) and t
OEZ
(max) define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
5. Either t
CDD
or t
ODD
must be satisfied.
6. t
OFF
is referenced from the rising edge of RAS or CAS , whichever is last.
Discontinued (9/98 - last order; 3/99 last ship)