參數(shù)資料
型號: IBM11N16845BB
廠商: IBM Microeletronics
英文描述: 16M x 72 Chip-Kill Protect ECC-on-DIMM Module(16M x 72 帶糾錯代碼保護的小外形雙列直插動態(tài)RAM模塊)
中文描述: 1,600 × 72片,殺死保護ECC的上內(nèi)存模塊(1,600 × 72帶糾錯代碼保護的小外形雙列直插動態(tài)內(nèi)存模塊)
文件頁數(shù): 4/29頁
文件大?。?/td> 502K
代理商: IBM11N16845BB
IBM11N16845BB
IBM11N16845CB
16M x 72 Chip-Kill Protect ECC-on-DIMM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 29
75H5487
GA14-4642-00
Revised 11/96
Truth Table
Function
RAS
CAS
WE
OE
Row
Address
Column
Address
DQx
Standby
H
H
X
X
X
X
X
High Impedance
Read
Early-Write
L
L
L
L
H
L
L
X
Row
Row
Col
Col
Valid Data Out
Valid Data In
Late-Write
L
L
H
L
H
L
H
Row
Col
Valid Data In
RMW
L
L
L
H
Row
Col
Valid Data In/Out
EDO Page Mode - Read 1st Cycle
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Row
Col
Valid Data Out
Subsequent Cycles
L
H
L
N/A
Col
Valid Data Out
EDO Page Mode - Write 1st Cycle
L
L
X
Row
Col
Valid Data In
Subsequent Cycles
L
L
X
N/A
Col
Valid Data In
EDO Page Mode - RMW 1st Cycle
L
H
L
H
L
L
H
L
H
Row
Col
Valid Data In/Out
Subsequent Cycles
L
N/A
Col
Valid Data In/Out
RAS-Only Refresh
L
H
X
X
Row
N/A
High Impedance
CAS-Before-RAS Refresh
H
L
L
H
X
X
X
High Impedance
Hidden Refresh
Read
L
H
L
L
H
L
Row
Col
Data Out
Write
L
H
L
L
H
X
Row
Col
Data In
Serial Presence Detect
SPD Entry
Value
SPD Entry
Binary
Bit4
Hex
Byte #
Description
Bit 7
Bit 6
Bit5
Bit3
Bit2
Bit1
Bit0
0
Number of SPD Bytes
128
1
0
0
0
0
0
0
0
80
08
02
0C
0D
0C
0B
01
48
00
01
3C
12
02
00
04
04
1
Total # Bytes in Serial PD
256
0
0
0
0
1
0
0
0
2
Memory Type
EDO
0
0
0
0
0
0
1
0
3
# of Row Addresses
12
0
0
0
0
1
1
0
0
13
0
0
0
0
1
1
0
1
4
# of Column Addresses
12
0
0
0
0
1
1
0
0
11
0
0
0
0
1
0
1
1
5
# of DIMM Banks
1
0
0
0
0
0
0
0
1
6
Module Data Width
x72
0
1
0
0
1
0
0
0
7
Module Data Width (Cont.)
0
0
0
0
0
0
0
0
0
8
Module Interface Levels
LVTTL
0
0
0
0
0
0
0
1
9
RAS Access
60ns
60
0
0
1
1
1
1
0
0
10
CAS Access
18ns
18
0
0
0
1
0
0
1
0
11
Dimm Config(Error Det/Corr.)
x72
ECC
0
0
0
0
0
0
1
0
12
Refresh Rate/Type
Normal 15.6
μ
s
x4
x4
0
0
0
0
0
0
0
0
13
Primary DRAM Organization
0
0
0
0
0
1
0
0
14
Secondary DRAM Organization
0
0
0
0
0
1
0
0
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