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| 型號： | IBM11N16845CB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 Chip-Kill Protect ECC-on-DIMM Module(16M x 72 帶糾錯代碼保護的小外形雙列直插動態(tài)RAM模塊) |
| 中文描述： | 1,600 × 72片，殺死保護ECC的上內(nèi)存模塊（1,600 × 72帶糾錯代碼保護的小外形雙列直插動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IBM11N16845CB |
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IBM11N16845BB
IBM11N16845CB
Preliminary
16M x 72 Chip-Kill Protect ECC-on-DIMM Module
75H5487
GA14-4642-00
Revised 11/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 29
Refresh Cycle
Symbol
Parameter
-6R
Unit
Notes
Min
Max
t
CHR
CAS Hold Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
CSR
CAS Setup Time
(CAS before RAS Refresh Cycle)
5
—
ns
t
WRP
WE Setup Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
WRH
WE Hold Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
RPC
RAS Precharge to CAS Hold Time
5
—
ns
t
REF
Refresh Period
13/11 addressing
—
64
ms
1
12/12 addressing
—
64
ms
2
1. 8192 refreshes are required every 64ms (13/11 addressing) for ROR; 4096 refreshes are required every 64ms for CBR.
2. 4096 refreshes are required every 64ms (12/12 addressing) for ROR or CBR.
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHZ
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
t
HD:STA
Start Condition Hold Time
4.0
t
LOW
Clock Low Period
4.7
t
HIGH
Clock High Period
4.0
t
SU:STA
Start Condition Setup Time(for a Repeated Start Condition)
4.7
t
HD:DAT
Data in Hold Time
0
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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