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參數(shù)資料
| 型號： | IBM11N2645H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 DRAM Module(2M x 64 動態(tài)RAM模塊) |
| 中文描述： | 200萬× 64內(nèi)存（2米× 64動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/31頁 |
| 文件大?。?/td> | 566K |
| 代理商： | IBM11N2645H |
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IBM11N2645H
IBM11N2735H
2M x 64/72 DRAM MODULE
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 31
50H7623.E93788
Released 5/98
Write Cycle
Symbol
Parameter
-50
-60
Unit
Notes
Min
Max
Min
Max
t
WCS
Write Command Set Up Time
0
—
0
—
ns
1
t
WCH
Write Command Hold Time
7
—
10
—
ns
t
WP
Write Command Pulse Width
7
—
10
—
ns
t
RWL
Write Command to RAS Lead Time
7
—
10
—
ns
t
CWL
Write Command to CAS Lead Time
7
—
10
—
ns
t
DS
D
IN
Setup Time
0
—
0
—
ns
2
t
DH
D
IN
Hold Time
7
—
10
—
ns
2
1. t
WCS
, t
RWD
, t
CWD
, and t
AWD
are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle; If t
RWD
≥
t
RWD
(min.), t
CWD
≥
t
CWD
(min.) and t
AWD
≥
t
AWD
(min.), the cycle is a Read-Modify-Write cycle and the data will
contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is
indeterminate.
2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE.
Discontinued (9/98 - last order; 3/99 last ship)
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