- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379204 > IBM11N4735CB (IBM Microeletronics) 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號： | IBM11N4735CB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| 中文描述： | 4米× 72內(nèi)存（4米× 72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 585K |
| 代理商： | IBM11N4735CB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
IBM11N4645BB
IBM11N4645CB
IBM11N4735BB
IBM11N4735CB
4M x 64/72 DRAM Module
50H8036.E22441E
Revised 5/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 31
AC Characteristics
(T
A
= 0 to +70
°
C, V
CC
=
3.3V
±
0.3V)
1. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and
V
IL
.
2. An initial pause of 200
μ
s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required..
3. AC measurements assume t
T
= 2ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-50
-60
Unit
Notes
Min
Max
Min
Max
t
RC
Random Read or Write Cycle Time
84
—
104
—
ns
t
RP
RAS Precharge Time
30
—
40
—
ns
t
CP
CAS Precharge Time
8
—
10
—
ns
t
RAS
RAS Pulse Width
50
10K
60
10K
ns
t
CAS
CAS Pulse Width
8
10K
10
10K
ns
t
ASR
Row Address Setup Time
0
—
0
—
ns
t
RAH
Row Address Hold Time
10
—
10
—
ns
t
ASC
Column Address Setup Time
0
—
0
—
ns
t
CAH
Column Address Hold Time
8
—
10
—
ns
t
RCD
RAS to CAS Delay Time
14
37
14
45
ns
1
t
RAD
RAS to Column Address Delay Time
12
25
12
30
ns
2
t
RSH
RAS Hold Time
8
—
10
—
ns
t
CSH
CAS Hold Time
43
—
50
—
ns
t
CRP
CAS to RAS Precharge Time
5
—
5
—
ns
t
ODD
OE to D
IN
Delay Time
15
—
15
—
ns
3
t
DZO
OE Delay Time from D
IN
0
—
0
—
ns
4
t
DZC
CAS Delay Time from D
IN
0
—
0
—
ns
4
t
T
Transition Time (Rise and Fall)
2
30
2
30
ns
1. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
2. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
3. Either t
CDD
or t
ODD
must be satisfied.
4. Either t
DZC
or t
DZO
must be satisfied.
Discontinued (9/98 - last order; 3/99 last ship)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM11N4845BB | 4M x 72 Chip-Kill Protect ECC-on-DIMM Module(4M x 72 帶糾錯代碼保護(hù)的小外形雙列直插動態(tài)RAM模塊) |
| IBM11N4845CB | 4M x 72 Chip-Kill Protect ECC-on-DIMM Module(4M x 72 帶糾錯代碼保護(hù)的小外形雙列直插動態(tài)RAM模塊) |
| IBM11N8645B | 8M x 64 DRAM MODULE(8M x 64動態(tài)RAM模塊) |
| IBM11N8645C | 8M x 64 DRAM MODULE(8M x 64動態(tài)RAM模塊) |
| IBM11N8735B | 8M x 72 DRAM MODULE(8M x 72動態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM14H5481 | 制造商:AVED Memory Products 功能描述: |
| IBM14H5540 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM17R8251 | 制造商:AVED Memory Products 功能描述: |
| IBM17R8252 | 制造商:AVED Memory Products 功能描述: |
| IBM1805T | 制造商:Schneider Electric 功能描述:IBM1805T |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。