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參數(shù)資料
| 型號(hào)： | IBM13M32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 441K |
| 代理商： | IBM13M32734BCA |
IBM13M32734BCA
Preliminary
32M x 72 2-Bank Registered SDRAM Module
19L7297.F38442A
4/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 24
AC Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 200
μ
s, with CKE0 held high, is required after power-up. A Precharge All Banks com-
mand must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode
Register Set operation.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1.2ns (1 Volt/ns rise time).
5. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback sig-
nal to its reference signal.
7. All timings are specified at the input receiver of the signal. This allows times to be specified at the end of
a transmission line versus at the DIMM connector which displays significant reflections. Refer to the
device specifications for non-skew adjusted timings.
AC Output Characteristics Diagram
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit
Discontinued (8/99 - last order; 12/99 - last ship)
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