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參數(shù)資料
| 型號： | IBM13M32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊內(nèi)存模塊（32M × 72配置2組寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 441K |
| 代理商： | IBM13M32734BCA |
IBM13M32734BCA
32M x 72 2-Bank Registered SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 24
19L7297.F38442A
4/99
Clock and Clock Enable Parameters
Symbol
Parameter
-75A max.
(Device CL
t
RCD
, t
RP
= 3, 3, 3)
Units
Notes
Min.
Max.
t
CK4
Clock Cycle Time, DIMM CAS Latency = 4
7.5
1000
ns
1
t
AC4
Clock Access Time, DIMM CAS Latency = 4
—
5.65
ns
1, 2
t
CKH
Clock High Pulse Width
2.5
—
ns
3
t
CKL
Clock Low Pulse Width
2.5
—
ns
3
t
CES
Clock Enable Setup Time
1.65
—
ns
1
t
CEH
Clock Enable Hold Time
0.35
—
ns
1
t
SB
Power Down Mode Entry Time
0
7.5
ns
t
T
Transition Time (Rise and Fall)
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode.
2. Access time is measured at 1.4V. See AC output load circuit.
3. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Discontinued (8/99 - last order; 12/99 - last ship)
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