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參數(shù)資料
| 型號： | IBM13M32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊內(nèi)存模塊（32M × 72配置2組寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 441K |
| 代理商： | IBM13M32734BCA |
IBM13M32734BCA
Preliminary
32M x 72 2-Bank Registered SDRAM Module
19L7297.F38442A
4/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 24
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0 - CK3
Input
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associ-
ated clock. CK0 drives the PLL. CK1, CK2 & CK3 are terminated.
CKE0
Input
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh
mode.
S0 - S3
Input
Active Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Physical Bank 0 is selected by S0 and S2; Bank 1 is selected by S0
and S3.
RAS, CAS
WE
Input
Active Lowbe executed by the SDRAM.
BA0, 1
Input
—
Selects which SDRAM bank of four is activated.
A0 - A9, A11
A10/AP
Input
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or
BA1. If AP is low, then BA0 and BA1 are used to define which bank to precharge.
DQ0 - DQ63,
CB0 - CB7
Input
Output
—
Data and Check Bit Input/Output pins.
DQMB0 -
DQMB7
Input
Active
High
The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high
impedance state when sampled high. In Read mode, DQMB has a latency of three clock cycles in
Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB
has a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high.
V
DD
, V
SS
Supply
Power and ground for the module.
REGE
Input
Active
High
(Register
Mode
Enable)
The Register Enable pin must be held high for proper registered mode operation (signals redriven
to the SDRAMs when the clock rises, and held valid until the next rising clock).
SA0 - 2
Input
—
These signals are tied at the system planar to either V
SS
or V
DD
to configure the SPD EEPROM.
SDA
Input
Output
—
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus time to V
DD
to act as a pull up.
SCL
Input
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
DD
to act as a pull up.
WP
Input
Active
High
This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the
SPD EEPROM.
Discontinued (8/99 - last order; 12/99 - last ship)
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