參數(shù)資料
型號: IBM13M32734BCB
廠商: IBM Microeletronics
英文描述: 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊)
中文描述: 32M × 72配置2,銀行注冊內(nèi)存模塊(32M × 72配置2組寄存同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 7/20頁
文件大?。?/td> 575K
代理商: IBM13M32734BCB
IBM13M32734BCB
32M x 72 2-Bank Registered SDRAM Module
19L7299.F38444A
8/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 20
27
Minimum Row Precharge Time (t
RP
)
20.0ns
14
28
Minimum Row Active to Row Active delay (t
RRD
)
15ns
0F
29
Minimum RAS to CAS delay (t
RCD
)
20.0ns
14
30
Minimum RAS Pulse width (t
RAS
)
45.0ns
2D
31
Module Bank Density
128MB
20
32
Address and Command Setup Time Before Clock
1.5ns
15
33
Address and Command Hold Time After Clock
0.8ns
08
34
Data Input Setup Time Before Clock
1.5ns
15
35
Data Input Hold Time After Clock
0.8ns
08
36 - 61
Reserved
Undefined
00
62
SPD Revision
JEDEC 2
02
63
Checksum for bytes 0 - 62
Checksum data
cc
3
64 - 71
Manufacturers’ JEDEC ID Code
IBM
A400000000000000
91
72
Assembly Manufacturing Location
Toronto, Canada
Vimercate, Italy
53
73 - 90
Assembly Part Number
ASCII ‘13M32734BC “R” -75AY
31334D33323733344243rr
373541592020
4, 5
91 - 92
Assembly Revision Code
“R” plus ASCII Blank
rr20
5
93 - 94
Assembly Manufacturing Date
Year/Week code
yyww
6, 7
95 - 98
Assembly Serial Number
Serial Number
ssssssss
8
99 - 125
Reserved
Undefined
Not Specified
126
Module Supports Clock Frequency
100MHz
64
9
127
Attributes for clock frequency defined in Byte 126
CLK0, CL = 3, C on AP
85
9
128 - 255
Open for Customer Use
Undefined
00
Serial Presence Detect
(Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD
Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 7.5ns (133MHz).
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-51 (Decimal) ‘ 01-34 (Hex).
7. yy = Binary coded decimal year code, 0-00 (Decimal) ‘ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
9. These values apply to PC100 applications only.
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IBM13M32734BCC 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊)
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