參數(shù)資料
型號(hào)： IBM13M32734BCC
廠商： IBM Microeletronics
英文描述： 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置2銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 13/19頁(yè)
文件大?。?/td> 388K
代理商： IBM13M32734BCC
IBM13M32734BCC
Preliminary
32M x 72 2 Bank Registered SDRAM Module
88H5165.E24449
4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 19
AC Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 200
μ
s, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed
by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1.2ns (1 Volt/ns rise time).
5. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.
Clock and Clock Enable Parameters (Registered Mode)
Symbol
Parameter
-360/-365/-370 max.
-10
Units
Notes
Device CL, t
RCD
, t
RP
= 3, 2, 2
Sort
Min.
Max.
Min.
Max.
t
CK4
Clock Cycle Time, DIMM CAS Latency = 4
10
1000
15
1000
ns
1
t
CK3
Clock Cycle Time, DIMM CAS Latency = 3
15
1000
15
1000
ns
1, 2
t
AC4
Clock Access Time, DIMM CAS Latency = 4
-360
—
7.7
—
9.7
ns
1, 3
-365
—
8.2
ns
-370
—
8.7
ns
t
AC3
Clock Access Time, DIMM CAS Latency = 3
-360
—
10.7
—
10.7
ns
1, 3
-365
—
11.2
ns
-370
—
11.7
ns
t
CKH
Clock High Pulse Width
3
—
3
—
ns
4
t
CKL
Clock Low Pulse Width
3
—
3
—
ns
4
t
CES
Clock Enable Set-up Time
2.0
—
2.0
—
ns
1
t
CEH
Clock Enable Hold Time
1.6
—
1.6
—
ns
1
t
SB
Power down mode Entry Time
0
10
0
10
ns
t
T
Transition Time (Rise and Fall)
0.5
10
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode.
2. For 66Mhz clock, DIMM CAS Latency = 3 is the standard application.
3. Access time is measured at 1.4V. See AC output load circuit.
4. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit for -360/-365/-370
Vtt=1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit for -10
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