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參數(shù)資料
| 型號： | IBM13M32734BCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2銀行注冊內存模塊（32M × 72配置2組寄存同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 388K |
| 代理商： | IBM13M32734BCC |
IBM13M32734BCC
32M x 72 2 Bank Registered SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 19
88H5165.E24449
4/98
33
Address and Command Hold Time After
Clock
-360, -365, -370
1.0ns
10
-10
Undefined
00
34
Data Input Setup Time Before Clock
-360, -365, -370
2.0ns
20
-10
Undefined
00
35
Data Input Hold Time After Clock
-360, -365, -370
1.0ns
10
-10
Undefined
00
36 - 61 Reserved
Undefined
00
62
SPD Revision
-360, -365, -370
PC100 1.2A
12
-10
01
01
63
Checksum for bytes 0 - 62
Checksum Data
cc
3
64 - 71 Manufacturers’ JEDEC ID Code
IBM
A400000000000000
91
72
Assembly Manufacturing Location
Toronto, Canada
Vimercate, Italy
53
73 - 90 Assembly Part Number
-360
ASCII ‘13M32734BC”R”-360Y’
31334D33323733344243rr2D33
36305A2020
31334D33323733344243rr2D33
3635592020
31334D33323733344243rr2D33
3730592020
31334D33323733344243rr2D31
3059202020
31334D33323733344243rr2D33
36305A2020
rr20
yyww
ssssssss
4, 5, 9
-365
ASCII ‘13M32734BC”R”-365Y’
-370
ASCII ‘13M32734BC”R”-370Y’
-10
ASCII ‘13M32734BC”R”-10Y’
-360
ASCII ‘13M32734BC”R”-360Z’
91 - 92 Assembly Revision Code
93 - 94 Assembly Manufacturing Date
95 - 98 Assembly Serial Number
99 -
125
“R” plus ASCII blank
Year/Week Code
Serial Number
5
6, 7
8
Reserved
Undefined
Not Specified
126
Module Supports this Clock Frequency
-360, -365, -370
100MHz
64
-10
66MHz
66
127
Attributes for clock frequency defined in
Byte 126
-360, -365, -370
CLK0, CL=3, ConAP
85
-10
CL = 2, 3
06
128 -
255
Open for Customer Use
Undefined
00
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time for the -360, -365, -370 is 10ns (100MHz), and for -10 is 15ns (66MHz).
3. cc = Checksum Data byte, 00-FF (Hex)
4. “R” = Alphanumeric revision code, A-Z, 0-9
5. rr = ASCII coded revision code byte “R”
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex)
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex)
8. ss = Serial number data byte, 00-FF (Hex)
9. This table displays an example of the Assembly Part Numbers available.
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