參數(shù)資料
型號： IBM13M32734BCD
廠商： IBM Microeletronics
英文描述： 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動態(tài)RAM模塊)
中文描述： 32M × 72配置2，銀行注冊/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動態(tài)內(nèi)存模塊）
文件頁數(shù)： 15/20頁
文件大?。?/td> 579K
代理商： IBM13M32734BCD
IBM13M32734BCD
32M x 72 2-Bank Registered/Buffered SDRAM Module
19L7143.E93758B
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 20
.
Common Parameters
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CS
Command Setup Time
Registered
2.0
2.0
2.0
ns
1, 2
Buffered
7.2
7.2
7.2
ns
t
CH
Command Hold Time
Registered
1.6
1.6
1.6
ns
1, 2
Buffered
0.2
0.2
0.2
ns
t
AS
Address and Bank Select Setup Time
Registered
2.0
2.0
2.0
ns
1, 2
Buffered
7.2
7.2
7.2
ns
t
AH
Address and Bank Select Hold Time
Registered
1.6
1.6
1.6
ns
1, 2
Buffered
0.2
0.2
0.2
ns
t
RCD
RAS to CAS Delay
2.0
2.0
2.0
ns
1
t
RC
Bank Cycle Time
70
70
90
ns
1
t
RAS
Active Command Period
50
100000
50
100000
60
100000
ns
1
t
RP
Precharge Time
20
20
30
ns
1
t
RRD
Bank to Bank Delay Time
20
20
30
ns
1
t
CCD
CAS to CAS Delay Time (Same Bank)
1
1
1
CLK
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the
number of clock cycles = specified value of timing/clock period (count fractions as a whole number).
2. The set up and hold times refer to the addition of the register. Note that although the Buffered set up times appear much greater,
there is no additional clock cycle as there is in Registered mode.
Mode Register Set Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
20
—
20
—
30
—
ns
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the
number of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Refresh Cycle
Symbol
Parameter
-260
-360
-10
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
REF
Refresh Period
—
64
—
64
64
ms
1, 2
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake
up” the device.
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料
PDF描述
IBM13M32734BCE 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動態(tài)RAM模塊)
IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動態(tài)RAM模塊)
IBM13M32734CCB 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動態(tài)RAM模塊)
IBM13M32734JCA 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊)
IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動態(tài)RAM模塊)
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