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參數(shù)資料
| 型號(hào)： | IBM13M32734BCD |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊(cè)/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 579K |
| 代理商： | IBM13M32734BCD |
IBM13M32734BCD
32M x 72 2-Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
19L7143.E93758B
2/99
Read Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
3.6
1.9
4.9
3
2
Max.
Min.
3.6
1.9
4.9
3
2
Max.
Min.
3.6
1.9
4.9
3
2
Max.
t
OH
t
LZ
t
HZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
ns
ns
ns
CLK
CLK
9.9
9.9
11.9
1
t
DQZ
DQM Data Out Disable Latency
Registered
Buffered
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
-10
Units
Min.
2.0
2.0
20
10
1
0
Max.
Min.
2.0
2.0
20
10
1
0
Max.
Min.
3.0
2.0
0
0
1
0
Max.
t
DS
t
DH
t
DDL2
t
DPL
Data In Setup Time
Data In Hold Time
Data Input to Precharge
Data input to Precharge
ns
ns
ns
ns
CLK
CLK
t
DQW
DQM Write Mask Latency
Registered
Buffered
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Parameter
Min.
Max.
100
100
3.5
Units
KHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
ns
ms
Notes
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
15
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (8/99 - last order; 12/99 - last ship)
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