參數(shù)資料
型號(hào)： IBM13M32734BCD
廠商： IBM Microeletronics
英文描述： 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置2，銀行注冊(cè)/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 579K
代理商： IBM13M32734BCD
IBM13M32734BCD
32M x 72 2-Bank Registered/Buffered SDRAM Module
19L7143.E93758B
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 20
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
0A
02
4800
01
A0
60
60
80
02
80
04
04
01
8F
04
06
01
01
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Assembly Voltage Interface Levels
SDRAM Device Cycle Time (CL = 3)
128
256
SDRAM
12
10
2
x72
LVTTL
10.0ns
6.0ns
6.0ns
8.0ns
ECC
6 - 7
8
9
1, 2
10
SDRAM Device Access Time from
Clock at CL=3
-260
-360
-10
11
12
13
14
15
16
17
18
19
20
Assembly Error Detection/Correction Scheme
Assembly Refresh Rate/Type
SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SR/1X(15.625us)
x4
x4
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Registered/Buffered with
PLL
Write-1/Read Burst, Pre-
charge All, Auto-Precharge
10.0ns
15.0ns
6.0ns
9.0ns
N/A
21
SDRAM Module Attributes
IF
22
SDRAM Device Attributes: General
0E
23
Minimum Clock Cycle at CLX-1 (CL = 2)
-260
-360, -10
-260
-360, -10
A0
F0
60
90
00
1, 2
24
Maximum Data Access Time (t
AC
) from
Clock at CLX-1 (CL = 2)
25
Minimum Clock Cycle Time at CLX-2 (CL = 1)
Maximum Data Access Time (t
AC
) from Clock at CLX-2
(CL = 1)
26
N/A
00
27
Minimum Row Precharge Time (t
RP
)
-260, -360
-10
20.0ns
30.0ns
20.0ns
20.0ns
30.0ns
14
1E
14
14
1E
28
Minimum Row Active to Row Active delay (t
RRD
)
29
Minimum RAS to CAS delay (t
RCD
)
-260, -360
-10
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns (100MHz) for the -260 and -360 and 15ns (66MHz) for the -10.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料
PDF描述
IBM13M32734BCE 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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IBM13M32734JCA 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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