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參數(shù)資料
| 型號： | IBM13M32734CCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 1 Bank Registered/Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置1銀行注冊/緩沖內(nèi)存模組（32M × 72配置1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 658K |
| 代理商： | IBM13M32734CCA |
IBM13M32734CCA
32M x 72 1 Bank Registered/Buffered SDRAM Module
09K3541.F38352
10/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 20
Functional Description and Timing Diagrams
Refer to the IBM 128Mb Synchronous DRAM Die Revision A datasheet (Document 33L8019) for the func-
tional description and timing diagrams for buffered-mode operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
Units
Notes
f
SCL
SCL Clock Frequency
—
100
KHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
—
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
—
μ
s
t
HD:STA
Start Condition Hold Time
4.0
—
μ
s
t
LOW
Clock Low Period
4.7
—
μ
s
t
HIGH
Clock High Period
4.0
—
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
—
μ
s
t
HD:DAT
Data in Hold Time
0
—
μ
s
t
SU:DAT
Data in Setup Time
250
—
ns
t
R
SDA and SCL Rise Time
—
1
μ
s
t
F
SDA and SCL Fall Time
—
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
—
μ
s
t
DH
Data Out Hold Time
300
—
ns
t
WR
Write Cycle Time
—
15
ms
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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