- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379204 > IBM13M32734CCB (IBM Microeletronics) 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號： | IBM13M32734CCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置1，銀行注冊/緩沖內(nèi)存模組（32M × 72配置1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 364K |
| 代理商： | IBM13M32734CCB |
IBM13M32734CCB
32M x 72 1-Bank Registered / Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 20
06K7740.H03381
04/00
Read Cycle
Symbol
Parameter
-75A
Units
Notes
Min.
2.45
0.6
3.6
3
Max.
t
OH
t
LZ
t
HZ3
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
ns
ns
ns
CLK
6.6
1
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-75A
Units
Min.
1.75
1.05
15
5
1
Max.
t
DS
t
DH
t
DPL
t
DAL3
t
DQW
Data In Setup Time
Data In Hold Time
Data input to Precharge
Data in to Active Delay (CAS Latency = 3)
DQM Write Mask Latency
ns
ns
ns
CLK
CLK
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Parameter
Min.
Max.
100
100
3.5
Units
KHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
ns
ms
Notes
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
15
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM13M32734JCA | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| IBM13M64734BCA | 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| IBM13M64734CCA | 64M x 72 2-Bank Registered/Buffered SDRAM Module(64M x 72 2組寄存/緩沖同步動態(tài)RAM模塊) |
| IBM13M64734HCA | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動態(tài)RAM模塊) |
| IBM13M8734HCB | 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM14H5481 | 制造商:AVED Memory Products 功能描述: |
| IBM14H5540 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM17R8251 | 制造商:AVED Memory Products 功能描述: |
| IBM17R8252 | 制造商:AVED Memory Products 功能描述: |
| IBM1805T | 制造商:Schneider Electric 功能描述:IBM1805T |
發(fā)布緊急采購，3分鐘左右您將得到回復。