參數(shù)資料
型號(hào)： IBM13M32734CCB
廠商： IBM Microeletronics
英文描述： 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置1，銀行注冊(cè)/緩沖內(nèi)存模組（32M × 72配置1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 364K
代理商： IBM13M32734CCB
IBM13M32734CCB
32M x 72 1-Bank Registered / Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
06K7740.H03381
04/00
The table below describes the DQ wiring information for each SDRAM on the DIMM. Note that the DQ wiring
is different from that described in the Block Diagram (Bank, x4 SDRAMs) on page 4.
Data Wiring Cross Reference
The table below describes the input wiring for each clock on the DIMM.
Clock Input Wiring
DQ SDRAM
Designator
DQ SDRAM
Pin Number
Device position to DIMM Tab Data I/O
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17
DQ0
5
3
7
11
15
CB2
18
23
27
31
32
36
40
45
CB5
48
52
56
60
DQ1
11
2
6
10
14
CB3
19
22
26
30
33
37
41
44
CB4
49
53
57
61
DQ2
44
1
5
9
12
CB0
17
21
25
29
34
38
42
46
CB7
50
54
58
62
DQ3
50
0
4
8
13
CB1
16
20
24
28
35
39
43
47
CB6
51
55
59
63
1. These numbers can be associated with the corresponding DIMM tab pin by referencing the DIMM connector pinout on page 3 of
this specification. Example: DQ14 at the DIMM tab (pin 19) is wired to SDRAM device position D3, pin 11.
Data Topology
CK0
CK1
CK2
CK3
PLL CLK Input
Pin 24
Termination RC
Termination RC
Termination RC
Clock Topology
TL0
TL1
Total
Unit
Min
Max
Min
Max
Min
Max
0.126
0.345
1.013
1.415
1.145
1.658
in.
SDRAM
Note: Transmission lines (“TL”) are represented as cylinders and
labeled with length designators. These are the only lines which
represent physical trace segments.
For more detailed topology information please refer to the cur-
rent PC133 SDRAM Registered DIMM specification.
22
±
5%
DIMM
Connector
TL1
TL0
CK0
10
CK1, CK2, and CK3
12pF
TL0
TL1
Unit
0.127
2.647
in.
10
DIMM
Connector
TL1
TL0
12pF
Phase Lock Loop
(PLL)
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