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| 型號： | IBM13M32734CCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置1，銀行注冊/緩沖內(nèi)存模組（32M × 72配置1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 364K |
| 代理商： | IBM13M32734CCB |
IBM13M32734CCB
32M x 72 1-Bank Registered / Buffered SDRAM Module
06K7740.H03381
04/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 20
The table below describes the address and control information for each signal on the DIMM. Note that sev-
eral signals are double loaded at the input of the register.
Register Input Wiring
Functional Description and Timing Diagrams
Refer to the IBM PC133 128Mb Synchronous DRAM data sheet (33L8019) for the functional description and
timing diagrams for SDRAM operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
Register Pin number
30
31
33
34
36
37
38
40
41
42
43
44
45
47
48
49
51
52
54
Register 1 Signal
CLK
CAS
RAS
A1
A0
A3
A2
A5
A4
A7
A6
A9
A8
BS0
A10
A11
BS1
CKE0
CKE0
Register 2 Signal
CLK
NC
NC
BS1
A11
A10
BS0
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
RAS
CAS
Register 3 Signal
CLK
DQMB0
DQMB4
DQMB1
DQMB5
NC
NC
S0
NC
WE
WE
NC
S2
DQMB6
DQMB2
NC
NC
DQMB7
DQMB3
Address/Control Signal Topology
Note: Each Signal has two register input loads with the exception of DQMBs and Chip Select which have one.
For more detailed topology information please refer to the current PC133 SDRAM Registered DIMM specification.
Register Input
Register Input
TL0
Unit
Min
Max
0.199
1.336
in.
DIMM
Connector
TL0
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