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參數(shù)資料
| 型號(hào)： | IBM13M32734JCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Two Bank Registered/Buffered SDRAM Module(64M x 64 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置兩個(gè)銀行的注冊(cè)/緩沖內(nèi)存模組（64米× 64 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 529K |
| 代理商： | IBM13M32734JCA |
IBM13M32734JCA
32M x 72 Two Bank Registered/Buffered SDRAM Module
09K3883.F38743
4/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 20
DC Output Load Circuit
Input/Output Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Symbol
Parameter
x72
Units
Notes
Min.
Max.
I
I(L)
Input Leakage Current, any input
(0.0V
≤
V
IN
≤
3.6V), All Other Pins
Not Under Test = 0V
Address and Control Inputs
10
10
μ
A
DQ0-63, CB0 - 7
-2
+2
I
O(L)
Output Leakage Current
(D
OUT
is disabled, 0.0V
≤
V
OUT
≤
3.6V)
DQ0-63, CB0 - 7
-2
+2
μ
A
SDA
-1
+1
V
OH
Output Level
Output “H” Level Voltage (I
OUT
= -2.0mA)
2.4
V
DD
V
1
V
OL
Output Level
Output “L” Level Voltage (I
OUT
= +2.0mA)
0.0
0.4
1. See DC output load circuit.
Output
1200
50pF
3.3 V
870
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
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