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參數(shù)資料
| 型號(hào)： | IBM13M64734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 64米× 72雙銀行注冊(cè)內(nèi)存模塊（64米× 72 2組帶寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 392K |
| 代理商： | IBM13M64734HCA |
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 22
06K8049.H03530
5/00
Common Parameters
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
CS
Command Setup Time
1.65
—
ns
1
t
CH
Command Hold Time
0.35
—
ns
1
t
AS
Address and Bank Select Setup Time
1.65
—
ns
1
t
AH
Address and Bank Select Hold Time
0.35
—
ns
1
t
RCD
RAS to CAS Delay
20
—
ns
1
t
RC
Bank Cycle Time
67.5
—
ns
1
t
RAS
Active Command Period
45
100000
ns
1
t
RP
Precharge Time
20
—
ns
1
t
RRD
Bank to Bank Delay Time
15
—
ns
1
t
CCD
CAS to CAS Delay Time (Same Bank)
1
—
CLK
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Mode Register Set Style
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
RSC
Mode Register Set Cycle Time
2
—
CLK
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Refresh Cycle
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ns
1, 2
t
REFI
Average Refresh Interval Time
—
7.813
μ
s
t
SREX
Self Refresh Exit Time
10
—
ns
3
1. 8192 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to ‘wake
up’ the device.
3. Self Refresh exit is asynchronous, requiring 10ns to ensure initiation. Self Refresh exit is complete in 10ns + t
RC
.
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