參數(shù)資料
型號(hào)： IBM13M64734HCA
廠商： IBM Microeletronics
英文描述： 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 64米× 72雙銀行注冊內(nèi)存模塊（64米× 72 2組帶寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁數(shù)： 17/22頁
文件大?。?/td> 392K
代理商： IBM13M64734HCA
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
06K8049.H03530
5/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 22
The table below describes the physical DQ wiring information for each SDRAM on the DIMM. Note that the
DQ wiring is different from that described in the Block Diagram on page 4; the DQs are scrambled within the
same device for wiring optimization.
Data Wiring Cross Reference
The table below describes the input wiring for each clock on the DIMM.
Clock Input Wiring
DQ SDRAM
Designator
DQ SDRAM
Pin Number
Device position to DIMM Tab Data I/O
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17
DQ0
2
7
38
15
47
CB2
55
23
63
31
0
33
8
41
CB1
48
16
55
25
DQ1
5
6
37
14
46
CB7
54
22
62
30
1
34
9
42
CB5
49
17
57
26
DQ2
8
5
36
13
45
CB3
53
21
61
29
2
35
10
40
CB4
50
18
58
27
DQ3
11
4
39
12
44
CB6
52
20
60
28
3
32
11
43
CB0
51
19
59
24
DQ4
44
3
32
11
43
CB0
51
19
59
24
4
39
12
44
CB6
52
20
60
28
DQ5
47
2
35
10
40
CB4
50
18
58
27
5
36
13
45
CB3
53
21
61
29
DQ6
50
1
34
9
42
CB5
49
17
57
26
6
37
14
46
CB7
54
22
62
30
DQ7
53
0
33
8
41
CB1
48
16
56
25
7
38
15
47
CB2
55
23
63
31
1. These numbers can be associated with the corresponding DIMM tab pin by referencing the DIMM connector pinout on page 3 of
this specification. Example: DQ14 at the DIMM tab (pin 19) is wired to both SDRAM device position D2, pin 5 and SDRAM D11,
pin 50.
Data Topology
CK0
CK1
CK2
CK3
PLL CLK Input
Pin 24
Termination RC
Termination RC
Termination RC
TL0
TL1
Total
Unit
Min
Max
Min
Max
Min
Max
0.126
0.345
1.013
1.415
1.145
1.658
in.
SDRAM
Note: Transmission lines (“TL”) are represented as cylinders and
labeled with length designators. These are the only lines which
represent physical trace segments.
For more detailed topology information please refer to the cur-
rent PC133 SDRAM Registered DIMM specification.
10
±
5%
DIMM
Connector
TL1
TL0
相關(guān)PDF資料
PDF描述
IBM13M8734HCB 8M x 72 1 Bank Registered SDRAM Module with PLL(8M x 72 1組帶鎖相環(huán)的寄存同步動(dòng)態(tài)RAM模塊)
IBM13M8734HCC 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M8734HCD 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13N16644HCB 16M x 64 Two-Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
IBM13N16734HCB 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
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