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參數(shù)資料
| 型號(hào)： | IBM13M8734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊(cè)/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 543K |
| 代理商： | IBM13M8734HCC |
IBM13M8734HCC
8M x 72 1 Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 21
19L7145.E93758B
2/99
Common Parameters
Sym-
bol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CS
Command Setup Time
Registered
2.0
2.0
2.0
ns
1, 2
Buffered
7.2
7.2
8.2
ns
t
CH
Command Hold Time
Registered
1.6
1.6
1.6
ns
1, 2
Buffered
0.2
0.2
0.2
ns
t
AS
Address and Bank Select Set-up Time
Registered
2.0
2.0
2.0
ns
1, 2
Buffered
7.2
7.2
8.2
ns
t
AH
Address and Bank Select Hold Time
Registered
1.6
1.6
1.6
ns
1, 2
Buffered
0.2
0.2
0.2
ns
t
RCD
RAS to CAS Delay
20
20
30
ns
1
t
RC
Bank Cycle Time
70
70
90
ns
1
t
RAS
Active Command Period
50
100000
50
100000
60
100000
ns
1
t
RP
Precharge Time
20
20
30
ns
1
t
RRD
Bank to Bank Delay Time
20
20
30
ns
1
t
CCD
CAS to CAS Delay Time (Same Bank)
1
1
1
CLK
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
2. The setup and hold times refer to the addition of the register. Note that although the Buffered setup times appear much greater,
there is no additional clock cycle as there is in Registered mode.
Mode Register Set Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
20
—
20
—
30
—
ns
Refresh Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
SREX
Self Refresh Exit Time
10
—
10
—
10
CLK
1
t
REF
Refresh Period
—
64
—
64
64
ms
1. 4096 cycles.
Discontinued (8/99 - last order; 12/99 - last ship)
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