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參數(shù)資料
| 型號(hào)： | IBM13M8734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊(cè)/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 5/21頁(yè) |
| 文件大?。?/td> | 543K |
| 代理商： | IBM13M8734HCC |
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IBM13M8734HCC
8M x 72 1 Bank Registered/Buffered SDRAM Module
19L7145.E93758B
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 21
Clock Wiring
10 Ohm
CK0
Clock Net Wiring (CK0):
IN
SDRAM
SDRAM
All PLL clock SDRAM loads are equal--
achieved in part through equal-length
wiring.
FDBK
IN
(PLL out to Feedback input)
10 0hms
CK1, CK2, and CK3
Terminated Clock Nets (CK1, CK2, CK3):
PCK
OUT1
TO
OUT3
24pF
OUT10
30pF
Phase
Lock
Loop
Notes:
SDRAM
OUT4
PCK
Register (1:1)
1. The PLL is programmed via a combination of
the feedback path and on-DIMM loading. PLL
feedback produces zero phase shift from the
delayed CK0 input.
2. Card wiring and capacitance loading variation:
±
100 ps.
3. Timing is based on a driver with a 1 Volt/ns
rise time.
4. Feedback CapacitorValve determined by PLL
phase characteristics.
One of three SDRAM outputs is shown.
Register (1:1)
Discontinued (8/99 - last order; 12/99 - last ship)
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