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參數(shù)資料
| 型號： | IBM13M8734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 543K |
| 代理商： | IBM13M8734HCC |
IBM13M8734HCC
8M x 72 1 Bank Registered/Buffered SDRAM Module
19L7145.E93758B
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 21
73 - 90 Assembly Part Number
-260
ASCII ‘13M8734HC”R”-
260T’
31334D383733344843rr
2D32363054202020
4, 5
-360
ASCII ‘13M8734HC”R”-
360T’
31334D383733344843rr
2D383054202020
-10
ASCII ‘13M8734HC”R”-
10T’
31334D383733344843rr
2D31305420202020
91 - 92 Assembly Revision Code
“R” plus ASCII blank
rr20
5
93 - 94 Assembly Manufacturing Date
Year/Week Code
yyww
6, 7
95 - 98 Assembly Serial Number
Serial Number
ssssssss
8
99 -
125
Reserved
Undefined
Not Specified
126
Module Supports this Clock Frequency
-260, -360
100MHz
64
-10
66MHz
66
127
Attributes for clock frequency defined in
Byte 126
-260, -360
CLK0, CL=3, ConAP
85
-10
CL = 2, 3
06
128 -
255
Open for Customer Use
Undefined
00
Serial Presence Detect (Part 3 of 3)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. Minimum application clock cycle time for the -260 and -360 is 10ns (100MHz), and for -10 is 15ns (66MHz).
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-53 (Decimal)
01-35 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
Discontinued (8/99 - last order; 12/99 - last ship)
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