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參數(shù)資料
| 型號： | IBM13M8734HCD |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 339K |
| 代理商： | IBM13M8734HCD |
IBM13M8734HCD
8M x 72 1 Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 21
19L7291.E93875A
8/99
AC Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 200
μ
s, with CKE0 held high, is required after power-up. A Precharge All Banks com-
mand must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode
Register Set operation.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1.2ns (1 Volt/ns rise).
5. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner
6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback sig-
nal to its reference signal.
AC Characteristics Diagrams
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit for -260 and -360
Vtt=1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit for -10
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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