參數(shù)資料
型號(hào)： IBM13M8734HCD
廠商： IBM Microeletronics
英文描述： 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 8米× 72 1銀行注冊(cè)/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 339K
代理商： IBM13M8734HCD
IBM13M8734HCD
8M x 72 1 Bank Registered/Buffered SDRAM Module
19L7291.E93875A
8/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 21
Clock and Clock Enable Parameters
Symbol
Parameter
-260, (Device CL,
t
RCD
, t
RP
= 2, 2, 2)
-360, (Device CL,
t
RCD
, t
RP
= 3, 2, 2)
-10
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CK4
Clock Cycle Time, DIMM CAS Latency = 4
Registered
10
1000
10
1000
15
1000
ns
1
t
CK3
Clock Cycle Time, DIMM CAS Latency = 3
Registered
10
1000
15
1000
15
1000
ns
1, 2
Buffered
10
1000
10
1000
15
1000
ns
t
CK2
Clock Cycle Time, DIMM CAS Latency = 2
Buffered
10
1000
15
1000
15
1000
ns
1
t
AC4
Clock Access Time, DIMM CAS Latency = 4
Registered
—
7.2
—
7.2
—
8.2
ns
1, 3
t
AC3
Clock Access Time, DIMM CAS Latency = 3
Registered
—
7.2
—
10.2
—
9.2
ns
1, 3
Buffered
—
7.2
—
7.2
—
9.2
ns
t
AC2
Clock Access Time, DIMM CAS Latency = 2
Buffered
—
7.2
—
10.2
—
9.2
ns
1, 3
t
CKH
Clock High Pulse Width
3
—
3
—
3
—
ns
4
t
CKL
Clock Low Pulse Width
3
—
3
—
3
—
ns
4
t
CES
Clock Enable Set-up Time
Registered
2.1
—
2.1
—
2.1
—
ns
1
Buffered
7.4
—
7.4
—
8.4
—
ns
t
CEH
Clock Enable Hold Time
Registered
1.5
—
1.5
—
1.5
—
ns
1
Buffered
0.0
—
0.0
—
0.0
—
ns
t
SB
Power Down mode Entry Time
0
10
0
10
0
10
ns
t
T
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode.
2. For 66Mhz clock, DIMM CAS Latency = 3 is the standard application.
3. Access time is measured at 1.4V. See AC output load circuit.
4. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse width
of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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