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參數(shù)資料
| 型號： | IBM13M8734HCD |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 17/21頁 |
| 文件大小： | 339K |
| 代理商： | IBM13M8734HCD |
IBM13M8734HCD
8M x 72 1 Bank Registered/Buffered SDRAM Module
19L7291.E93875A
8/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 21
Read Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
3.6
3.6
3.6
ns
1
t
LZ
Data Out to Low Impedance Time
0.6
0.6
0.6
ns
t
HZ3
Data Out to High Impedance Time
3.6
7.2
3.6
7.2
3.6
7.2
ns
1
t
HZ2
Data Out to High Impedance Time
3.6
7.2
3.6
9.2
3.6
9.2
ns
1
t
DQZ
DQM Data Out Disable Latency
Registered
3
3
3
CLK
Buffered
2
2
2
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
DS
Data In Setup Time
2.1
2.1
3.1
ns
t
DH
Data In Hold Time
1.6
1.6
1.6
ns
t
DPL
Data Input to Precharge
15
15
15
ns
t
DAL3
Data into Active Delay (CAS Latency = 3)
5
5
5
CLK
t
DAL2
Data into Active Delay (CAS Latency = 2)
4
4
4
CLK
t
DQW
DQM Write Mask Latency
Registered
1
1
1
CLK
Buffered
0
0
0
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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