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參數(shù)資料
| 型號： | IBM13N16644HC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 2 Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 16米x 64 2行無緩沖內(nèi)存模組（16米x 64 2組不帶緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 651K |
| 代理商： | IBM13N16644HC |
IBM13N16644HC
IBM13N16734HC
16M x 64/72 2 Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 18
19L7123.E93760A
2/99
Mode Register Set Cycle
Symbol
Parameter
-260
(CL, t
RCD
, t
RP
= 2/ 2 / 2
)
-360
(CL, t
RCD
, t
RP
= 3 / 2 / 2
)
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
20
—
20
—
20
—
ns
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
Symbol
Parameter
-260
(CL, t
RCD
, t
RP
= 2/ 2 / 2
)
-360
(CL, t
RCD
, t
RP
= 3 / 2 / 2)
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
3
—
3
—
3
—
ns
t
LZ
Data Out to Low Impedance Time
0
—
0
—
0
—
ns
t
HZ3
Data Out to High Impedance
Time
3
6
3
6
3
8
ns
1
t
HZ2
Data Out to High Impedance
Time
3
6
3
8
3
8
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
-260
(CL, t
RCD
, t
RP
= 2/ 2 / 2
)
-360
(CL, t
RCD
, t
RP
= 3 / 2 / 2)
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
REF
Refresh Period
—
64
—
64
—
64
ms
1
t
SREX
Self Refresh Exit Time
10
10
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-260
(CL, t
RCD
, t
RP
= 2/ 2 / 2
)
-360
(CL, t
RCD
, t
RP
= 3 / 2 / 2)
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
DS
Data In Set-up Time
2
—
2
—
3
—
ns
t
DH
Data In Hold Time
1
—
1
—
1
—
ns
t
DPL3
Data Input to Precharge
10
—
10
—
10
—
ns
t
DPL2
Data Input to Precharge
10
—
15
—
15
—
ns
t
DQW
DQM Write Mask Latency
0
—
0
—
0
—
CLK
Discontinued 8/99 ast rder; 2/99 ast hip)
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| IBM13N16734HC | 16M x 72 2 Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動態(tài)RAM模塊) |
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