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參數(shù)資料
| 型號： | IBM13N16644HCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 Two-Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 1,600 × 64雙行緩沖內(nèi)存模組（16米x 64 2組不帶緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 331K |
| 代理商： | IBM13N16644HCB |
IBM13N16644HCB
IBM13N16734HCB
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 18
09K3605.F38386
12/99
Clock and Clock Enable Parameters
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
CK3
Clock Cycle Time, CAS Latency = 3
7.5
1000
ns
t
AC3
Clock Access Time, CAS Latency = 3
—
5.4
ns
1
t
CKH
Clock High Pulse Width
2.5
—
ns
2
t
CKL
Clock Low Pulse Width
2.5
—
ns
2
t
CES
Clock Enable Set-up Time
1.5
—
ns
t
CEH
Clock Enable Hold Time
0.8
—
ns
t
SB
Power down mode Entry Time
0
7.5
ns
t
T
Transition Time (Rise and Fall)
0.5
10
ns
1. Access time is measured at 1.4V. In AC Characteristics section, see notes.
2. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
Common Parameters
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
CS
Command Setup Time
1.5
—
ns
t
CH
Command Hold Time
0.8
—
ns
t
AS
Address and Bank Select Set-up Time
1.5
—
ns
t
AH
Address and Bank Select Hold Time
0.8
—
ns
t
RCD
RAS to CAS Delay
20.0
—
ns
1
t
RC
Bank Cycle Time
67.5
—
ns
1
t
RAS
Active Command Period
45
100000
ns
1
t
RP
Precharge Time
20.0
—
ns
1
t
RRD
Bank to Bank Delay Time
15
—
ns
1
t
CCD
CAS to CAS Delay Time
1
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
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