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參數(shù)資料
| 型號(hào)： | IBM13N16644HCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 Two-Bank Unbuffered SDRAM Module(16M x 64 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 1,600 × 64雙行緩沖內(nèi)存模組（16米x 64 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 331K |
| 代理商： | IBM13N16644HCB |
IBM13N16644HCB
IBM13N16734HCB
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 18
09K3605.F38386
12/99
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Note
s
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on Assembly
12
0C
4
Number of Column Addresses on Assembly
9
09
5
Number of DIMM Banks
2
02
6 - 7
Data Width of Assembly
16M x 64
x64
4000
16M x 72
x72
4800
8
Voltage Interface Level of this Assembly
LVTTL
01
9
SDRAM Device Cycle Time at CL=3
7.5ns
75
10
SDRAM Device Access Time from Clock at CL=3
5.4ns
54
1
11
DIMM Configuration Type
16M x 64
Non-Parity
00
16M x 72
ECC
02
12
Refresh Rate/Type
SR/1x(15.625us)
80
13
Primary SDRAM Device Width
x8
08
14
Error Checking SDRAM Device Width
16M x 64
N/A
00
16M x 72
x8
08
15
SDRAM Device Attr: Min Clk Delay, Random Col
Access
1 Clock
01
16
SDRAM Device Attributes: Burst Lengths Supported
1,2,4,8, Full Page
8F
17
SDRAM Device Attributes: Number of Device Banks
4
04
18
SDRAM Device Attributes: CAS Latencies Supported
2, 3
06
19
SDRAM Device Attributes: CS Latency
0
01
20
SDRAM Device Attributes: WE Latency
0
01
21
SDRAM Module Attributes
Unbuffered
00
22
SDRAM Device Attributes: General
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, V
DD
+/- 10%
15.0ns
0E
23
Minimum Clock Cycle at CL=2
F0
24
Maximum Data Access Time (t
AC
) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
9.0ns
90
1
25
N/A
00
26
Maximum Data Access Time (t
AC
) from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
N/A
00
27
20ns
14
28
15ns
0F
29
20ns
14
30
45ns
2D
1. See the AC output load circuit in the AC Characteristics section below
2. cc = Checksum Data byte, 00-FF (Hex)
3. “R” = Alphanumeric revision code, A-Z, 0-9
4. rr = ASCII coded revision code byte “R”
5. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex)
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex)
7. ss = Serial number data byte, 00-FF (Hex)
8. For PC100 applications only.
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| IBM13N16734HCB | 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
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