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參數(shù)資料
| 型號： | IBM13N16734HC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 2 Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 16米x 72 2行無緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 651K |
| 代理商： | IBM13N16734HC |
IBM13N16644HC
IBM13N16734HC
16M x 64/72 2 Bank Unbuffered SDRAM Module
19L7123.E93760A
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 18
Serial PD Device Active Power
Supply Current
I
CCA
SCL Clock Frequency =
100KHz
1
1
1
1
mA
10
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed/Organization
Units
Notes
-260, -360/x64 -10/x64 -260, -360/x72 -10/x72
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I
CC3N
).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t
ck(min)
.
9. V
DD
= 3.3V.
10. As follows:
Input pulse levels V
DD
x 0.1 to V
DD
x 0.9
Input rise and fall times 10ns
Input and output timing levels V
DD
x 0.5
Output load 1 TTL gate and CL=100pf
Discontinued (8/99 - last order; 12/99 - last ship)
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