參數(shù)資料
型號(hào)： IBM13N16734HC
廠商： IBM Microeletronics
英文描述： 16M x 72 2 Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 16米x 72 2行無(wú)緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 12/18頁(yè)
文件大小： 651K
代理商： IBM13N16734HC
IBM13N16644HC
IBM13N16734HC
16M x 64/72 2 Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 18
19L7123.E93760A
2/99
AC Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
An initial pause of 200
μ
s, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Precharge All Banks
command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set
operation.
1. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
2. In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
3. Load Circuit A: AC timing tests have V
IL
= 0.4 V and V
IH
= 2.4 V with the timing referenced to the 1.40V crossover point
4. Load Circuit A: AC measurements assume t
T
=1.0 ns.
5. Load Circuit B: AC timing tests have V
IL
= 0.8 V and V
IH
= 2.0 V with the timing referenced to the 1.40V crossover point
6. Load Circuit B: AC measurements assume t
T
=1.2 ns.
AC Characteristics Diagrams
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
1.4V
V
IL
1.4V
t
T
Vtt=1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit (A)
t
CKH
t
CKL
Output
50pF
Z
o
= 50
AC Output Load Circuit (B)
V
IH
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料
PDF描述
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