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參數(shù)資料
| 型號(hào)： | IBM13N16734HCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 1,600 × 72雙行緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 331K |
| 代理商： | IBM13N16734HCB |
IBM13N16644HCB
IBM13N16734HCB
16M x 64/72 Two-Bank Unbuffered SDRAM Module
09K3605.F38386
12/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 18
Features
168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
16Mx64/72 Synchronous DRAM DIMM
Intended for PC133 applications
Clock Frequency: 133MHz
Clock Cycle: 7.5ns
Clock Assess Time: 5.4ns
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have 4 internal banks
Module has 2 Physical banks
Fully Synchronous to positive Clock Edge
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge commands
Programmable Operation:
- CAS Latency: 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Suspend Mode and Power Down Mode
12/9/2 Addressing (Row/Column/Bank)
4096 Refresh cycles distributed across 64ms
Serial Presence Detect with Write Protect
Card size: 5.25" x 1.375" x 0.158" max
Gold contacts
DRAMs in TSOP Type II Package
Description
IBM13N16644HCB / IBM13N16734HCB are unbuf-
fered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
16Mx64 and 16Mx72 high-speed memory arrays
and are configured as two 8M x 64/72 physical
tanks. The DIMMs use sixteen (16Mx64) or eigh-
teen(16Mx72) 8Mx8 SDRAMs in 400mil TSOP II
packages. The DIMMs achieve high-speed data-
transfer rates of up to 133MHz by employing a
prefetch/pipeline hybrid architecture that supports
the JEDEC 1N rule while allowing very low burst
power.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0 - CK3). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0-S3, DQMB, and CKE0-CKE1 signals.
A command decoder initiates the necessary timings
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
.
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