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參數(shù)資料
| 型號： | IBM13Q32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Registered SDRAM Module(32M x 72 200腳寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置注冊內(nèi)存模塊（32M × 72配置200腳寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 247K |
| 代理商： | IBM13Q32734BCA |
IBM13Q32734BCA
32M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 15
04K8918.C75665B
6/99
Mode Register Set Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
RSC
Mode Register Set Cycle Time
20
—
ns
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3.3
—
ns
t
LZ
Data Out to Low Impedance Time
0.3
—
ns
t
HZ2
Data Out to High Impedance Time
3.3
10.8
ns
1
t
DQZ
DQM Data Out Disable Latency
3
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ms
1
t
SREX
Self Refresh Exit Time
10
—
ns
1. 4096 cycles.
Write Cycle
Symbol
Parameter
Value
Units
Min.
Max.
t
DS
Data In Setup Time
3.3
—
ns
t
DH
Data In Hold Time
2.3
—
ns
t
DPL2
Data input to Precharge
1
—
CLK
t
DQW
DQM Write Mask Latency
1
—
CLK
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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