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參數(shù)資料
| 型號(hào)： | IBM13Q32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Registered SDRAM Module(32M x 72 200腳寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置注冊(cè)內(nèi)存模塊（32M × 72配置200腳寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 247K |
| 代理商： | IBM13Q32734BCA |
IBM13Q32734BCA
32M x 72 Registered SDRAM Module
04K8918.C75665B
6/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 15
Functional Description and Timing Diagram
Refer to IBM 200-pin SDRAM Registered DIMM Functional Description and Timing Diagram
(Document 04K8917.C75644C, for SDRAM operation).
Clock Frequency and Latency
Symbol
Parameter
Value
Units
Notes
f
CK
Clock Frequency
66.667
MHz
t
CK
Clock Cycle Time
15
ns
t
AA
CAS Latency
3
t
CK
1
t
RCD
RAS to CAS Delay
2
t
CK
t
RC
Bank Cycle Time
6
t
CK
t
RAS
Minimum Bank Active Time
4
t
CK
t
RP
Precharge Time
2
t
CK
t
DPL
Data In to Precharge
1
t
CK
t
DAL
Data In to Active/Refresh
3
t
CK
t
RRD
Bank to Bank Delay Time
2
t
CK
t
CCD
CAS to CAS Delay Time
1
t
CK
t
WL
Write Latency
1
t
CK
t
DQW
DQM Write Mask Latency
1
t
CK
t
DQZ
DQM Data Disable Latency
3
t
CK
t
CSL
Clock Suspend Latency
1
t
CK
1. SDRAMs have t
AA
=2, but on-board DIMM register adds one clock cycle
Presence Detect Read Cycle
Symbol
Parameter
Value
Unit
Notes
Min
Max
t
PD
PDE to Valid Presence Detect Data
—
10
ns
1
t
PDOFF
PDE Inactive to Presence Detects Inactive
0
10
ns
2
1. Measured with the specified current load and 100pF.
2. t
PDOFF
(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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